Earliest possible GPIO toggle on i.mx6

[Mayur Nande]

Hello all,

I have a question regarding the earliest possible GPIO toggle with barebox on imx6. We use boards with imx6 quad core processor (from Phytec). In our hardware design we have a push button controller which has a "KILL" pin attached to one of the GPIO pins on i.mx6. The requirement is that this pin should be set to 1 within 400 ms of power on. I tried setting this at various places in barebox with incremental improvements starting from the init script, board.c, lowlevel.c and then DCD/lowlevel.c combination.

The best performance I got was by setting the iomux registers (IOMUXC_SW_MUX_CTL_PAD and IOMUXC_SW_PAD_CTL_PAD) in DCD and the GPIO direction and value registers in lowlevel.c (since GPIO controller registers are not accessible with DCD). Even with this, I get the GPIO set in around 460-475ms at the best. I understand that some of the time here is used by the hardware for voltage regulation/crystal stabilization which probably we can't do anything about.

From barebox side, any suggestions or ideas to improve this would be very helpful.
Thank you very much.

Warm Regards,
Mayur Nande

[Lucas Stach]

Post by Mayur Nande
Hello all,
I have a question regarding the earliest possible GPIO toggle with
barebox on imx6. We use boards with imx6 quad core processor (from
Phytec). In our hardware design we have a push button controller which
has a "KILL" pin attached to one of the GPIO pins on i.mx6. The
requirement is that this pin should be set to 1 within 400 ms of power
on. I tried setting this at various places in barebox with incremental
improvements starting from the init script, board.c, lowlevel.c and
then DCD/lowlevel.c combination.
The best performance I got was by setting the iomux registers
(IOMUXC_SW_MUX_CTL_PAD and IOMUXC_SW_PAD_CTL_PAD) in DCD and the GPIO
direction and value registers in lowlevel.c (since GPIO controller
registers are not accessible with DCD). Even with this, I get the GPIO
set in around 460-475ms at the best. I understand that some of the
time here is used by the hardware for voltage regulation/crystal
stabilization which probably we can't do anything about.

If lowlevel.c is too late already, the only chance to make this work is
setting the DCD padctl to configure a pull-up/down to satisfy the KILL
pin. Then in the board file set up the GPIO and switch the padctl to
neutral state.

Still 400ms sound like a awfully long time to reach lowlevel init. What
is your boot source, i.e. where is the barebox binary stored?

Regards,
Lucas

[Mayur Nande]

Hello Lucas,

Thank you for the reply.

-----Original Message-----
Sent: Wednesday, July 05, 2017 2:52 PM
To: Mayur Nande
Subject: Re: Earliest possible GPIO toggle on i.mx6

Post by Mayur Nande
Hello all,
I have a question regarding the earliest possible GPIO toggle with
barebox on imx6. We use boards with imx6 quad core processor (from
Phytec). In our hardware design we have a push button controller which
has a "KILL" pin attached to one of the GPIO pins on i.mx6. The
requirement is that this pin should be set to 1 within 400 ms of power
on. I tried setting this at various places in barebox with incremental
improvements starting from the init script, board.c, lowlevel.c and
then DCD/lowlevel.c combination.
The best performance I got was by setting the iomux registers
(IOMUXC_SW_MUX_CTL_PAD and IOMUXC_SW_PAD_CTL_PAD) in DCD

and the GPIO

Post by Mayur Nande
direction and value registers in lowlevel.c (since GPIO controller
registers are not accessible with DCD). Even with this, I get the GPIO
set in around 460-475ms at the best. I understand that some of the
time here is used by the hardware for voltage regulation/crystal
stabilization which probably we can't do anything about.

If lowlevel.c is too late already, the only chance to make this work is setting
the DCD padctl to configure a pull-up/down to satisfy the KILL pin. Then in
the board file set up the GPIO and switch the padctl to neutral state.

Ok, I will try this.

Still 400ms sound like a awfully long time to reach lowlevel init. What is your
boot source, i.e. where is the barebox binary stored?

The bootsource is external 8GB SD/MMC card.

Warm Regards,
Mayur

[Mayur Nande]

-----Original Message-----
From: Mayur Nande
Sent: Wednesday, July 05, 2017 3:18 PM
To: 'Lucas Stach'
Subject: RE: Earliest possible GPIO toggle on i.mx6
Hello Lucas,
Thank you for the reply.

-----Original Message-----
Sent: Wednesday, July 05, 2017 2:52 PM
To: Mayur Nande
Subject: Re: Earliest possible GPIO toggle on i.mx6

Post by Mayur Nande
Hello all,
I have a question regarding the earliest possible GPIO toggle with
barebox on imx6. We use boards with imx6 quad core processor (from
Phytec). In our hardware design we have a push button controller
which has a "KILL" pin attached to one of the GPIO pins on i.mx6.
The requirement is that this pin should be set to 1 within 400 ms of
power on. I tried setting this at various places in barebox with
incremental improvements starting from the init script, board.c,
lowlevel.c and then DCD/lowlevel.c combination.
The best performance I got was by setting the iomux registers
(IOMUXC_SW_MUX_CTL_PAD and IOMUXC_SW_PAD_CTL_PAD) in DCD

and the GPIO

Post by Mayur Nande
direction and value registers in lowlevel.c (since GPIO controller
registers are not accessible with DCD). Even with this, I get the
GPIO set in around 460-475ms at the best. I understand that some of
the time here is used by the hardware for voltage regulation/crystal
stabilization which probably we can't do anything about.

If lowlevel.c is too late already, the only chance to make this work
is setting the DCD padctl to configure a pull-up/down to satisfy the
KILL pin. Then in the board file set up the GPIO and switch the padctl to

neutral state.
Ok, I will try this.

I tried this, but unfortunately none of the available internal pull-up and pull-down
values satisfy the KILL pin (it goes through an digital isolator and we cannot satisfy
the logic level it asks for). The only way is to set the pin as output.

Still 400ms sound like a awfully long time to reach lowlevel init.
What is your boot source, i.e. where is the barebox binary stored?

The bootsource is external 8GB SD/MMC card.

I also tried the internal emmc just as an experiment and the delay is nearly the same.

I have some suggestions from Chris Healy like trying SPI NOR and using the fast boot bit of SDHC,
I will try that as my next steps. The final (non-preferred) solution would be to change the hardware.

Thank you.

Regards
Mayur